-Moves and Conditional Moves

15.5 FPU Instructions

Moves and Conditional Moves

The only legal formats for the move and conditional move instructions are single and double precision. The move instructions do not trap if their operands are either denormalized or NaNs, which is consistent with the R4400 implementation. Execution of floating-point move and conditional move instructions do not affect the Cause field of the floating-point Status register unless they take an Unimplemented Operation exception because an illegal formats was used.*1

The upper 32 bits of the destination registers are undefined in architecture for all the floating-point arithmetic operations in single-precision or 32-bit fixed format (S or W). In the R10000 processor, the implementation clears the upper 32 bits, including MOV.S, whereas R4400 and R4200 processors preserve the upper 32 bits during the move.

For the floating-point conditional move instructions, MOVT.S, MOVF.S, MOVZ.S, and MOVN.S, the R10000 processor always clears the upper 32 bits of the destination register even though the condition is false.

In 32 floating-point register mode (FR=1), the upper 32 bits of the destination register for the MTC1 and LWC1 instructions are architecturally undefined. The R10000 processor implementation clears the upper 32 bits.

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